As a semiconductor device becomes more highly integrated, a design rule is reduced. As the design rule reduces, technology development of a highly integrated semiconductor memory device, for example, a dynamic random access memory (DRAM) device reaches a limit. Accordingly, research to reduce a unit area of a cell storing one bit is in progress.
A more highly integrated cell structure may be formed by realizing a 1K unit cell in 6F2 and 4F2, rather than 8F2, which is a general reference storing one bit However, us a 4F2 transistor to form a more highly integrated cell remains under development.
For manufacturing a 4F2 transistor, the source region and the drain region of a cell transistor, that is, the source region in a capacitor forming region where charges are stored, and the drain region discharging charges to a bit line should be manufactured in 1F2. For this purpose, research on a vertical type cell transistor structure where a source region and a drain region can be manufactured in 1F2 is being considered. The vertical type cell transistor has a structure in which the source region and the drain region of the transistor that operate a cell are formed up and down. The vertical pole type channel operates the transistor. That is, the operation of a 1K cell transistor can be realized within 4F2 by vertically forming, in the upper and lower portions, the source region and the drain region that have been formed in a horizontal shape in 8F2. However, as a level of difficulty increases in a vertical type cell transistor structure, it is difficult to predict the possible structure formations. Also, since a bit line is formed under the transistor, a considerable difficulty is expected in securing resistance and storage capacity of the bit line. Since the bit line should be formed by the source region and the drain region in the upper and lower portions, the bit line must be formed in the lower portion. However, this lower bit line cannot be formed in a metal stack structure. Therefore, for the bit line, an n-type impurity implanted silicon electrode is used or saliside formed through reaction with Si is used to overcome high resistance. Also, a cell region and a peripheral circuit region should be independently formed because of an integration difference between the cell region and the peripheral circuit region. That is, since the number of processes greater than the number of conventional processes is used, a process operation is complicated.